GOA (Gate Driver on Array, row scanning integrated on an array substrate) is a technology of manufacturing a row-scanning gate driving circuit on the array substrate by utilizing an existing TFT-LCD (Thin Film Transistor-Liquid Crystal Display) array process, carrying out progressive scan driving for gate lines. The GOA technology can reduce bonding procedures in connecting to an external IC (Integrated Circuit), has an opportunity to increase product yield and alter the cost, and can make a liquid crystal display panel become more suitable for manufacturing a display product with narrow bezel or without bezel.
As with the development of LTPS (Low Temperature Poly-silicon) semiconductor thin-film transistors, LTPS-TFT liquid crystal displays gather more and more attention. The LTPS-TFT liquid crystal displays have advantages including high resolution, fast in response, high brightness, and high aperture ratio. Also, since LTPS semiconductor itself possesses super high carrier mobility, the GOA technology may be adopted to manufacture a gate driver on a thin-film transistor array substrate to carry out the objective of system integration, save the space, and reduce the cost of driving ICs. In order to assure the stability of an output terminal G(n), two nodes Q(n) and P(n) generally are introduced. The point Q(n) is configured to control the output of a gate driving signal; and the point P(n) is configured to maintain the stability of low voltage levels of the Q(n) point and the output terminal G(n). Mutual restriction exists between the two nodes Q(n) and P(n).
Please refer to FIG. 1, which is a schematic diagram showing a GOA electric circuit based on LTPS semiconductor thin-film transistors in the existing skills. The GOA electric circuit comprises a plurality of cascaded GOA units. Assuming that n is a positive integer, the nth-stage GOA unit comprises a first thin-film transistor T1 having a gate electrode electrically connected to a first clock signal CK1, a source electrode electrically connected to an output terminal G(n−1) of a previous-stage (the (n−1)th stage) GOA unit, and a drain electrode electrically connected to a third node K(n); a second thin-film transistor T2 having a gate electrode electrically connected to a first node Q(n), a source electrode electrically connected to a second clock signal CK2, and a drain electrode electrically connected the an output terminal G(n); a third thin-film transistor T3 having a gate electrode electrically connected to a third clock signal CK3, a source electrode electrically connected to an output terminal G(n+1) of a next-stage (the (n+1)th stage) GOA unit, and a drain electrode electrically connected to the third node K(n); a fourth thin-film transistor T4 having a gate electrode electrically connected to a fourth clock signal CK4, a source electrode electrically connected to a constant low voltage level VGL, and a drain electrode electrically connected to the output terminal G(n); a fifth thin-film transistor T5 having a gate electrode electrically connected to a constant high voltage level VGH, a source electrode electrically connected to the third node K(n), and a drain electrode electrically connected to the first node Q(n); a sixth thin-film transistor T6 having a gate electrode electrically connected to a second node P(n), a source electrode electrically connected to the constant low voltage level VGL, and a drain electrode electrically connected to the third node K(n); a seventh thin-film transistor T7 having a gate electrode electrically connected to the second node P(n), a source electrode electrically connected to the constant low voltage level VGL, and a drain electrode electrically connected to the output terminal G(n); an eighth thin-film transistor T8 having a gate electrode electrically connected to the third node K(n), a source electrode electrically connected to the constant low voltage level VGL, and a drain electrode electrically connected to the second node P(n); a ninth thin-film transistor T9 having a gate electrode and a source electrode, both of which are electrically connected to the second clock signal CK2, and a drain electrode electrically connected to the second node P(n); a bootstrap capacitor C1, one terminal of which is electrically connected to the first node Q(n) and the other terminal of which is electrically connected to the output terminal G(n); and a second capacitor C2, one terminal of which is electrically connected to the second node P(n) and the other terminal of which is electrically connected to the constant low voltage level VGL.
The GOA electric circuit shown in FIG. 1 can not only perform a forward scanning but also a backward scanning. The processes of the forward scanning and the backward scanning are similar to each other. The following is described with the forward scanning as an example wither referring to FIG. 1 and FIG. 2. FIG. 2 is a timing chart of a forward scanning in the GOA electric circuit based on LTPS semiconductor thin-film transistors shown in FIG. 1 in the existing skills. The processes of the forward scanning are described below. Stage I (pre-charging): both of G(n−1) and CK1 are at high voltage level, T1 is turned on, the gate electrode of T5 is connected to the constant high voltage level VGH and thus T5 is always in a turned-on state, and the first node Q(n) is pre-charged to high voltage level. Stage II (the output terminal G(n) outputs high voltage level): G(n−1) and CK1 are changed to low voltage level, CK2 provides high voltage level, the first node Q(n) is maintained at high voltage level due to the storage function of the bootstrap capacitor C1, T2 is turned on, the high voltage level of CK2 is outputted to the output terminal G(n) and thus the output terminal G(n) outputs high voltage level and this makes the first node Q(n) be pulled up to a higher voltage level, and meanwhile, T8 is turned on, the voltage level of the second node P(n) is pulled down, and T6 and T7 is turned off. Stage III (the output terminal G(n) outputs low voltage level): both of CK3 and G(n+1) provide high voltage level, the first node Q(n) is still at high voltage level, CK2 is changed to low voltage level, the low voltage level of CK2 is outputted to the output terminal G(n), and thus the output terminal G(n) outputs low voltage level. Stage IV (the first node Q(n) is pulled down to the constant low voltage level VGL): CK1 provides high voltage level again, G(n−1) is maintained at low voltage level, T1 is turned on to pull down the voltage level of the first node Q(n) to the constant low voltage level VGL, and T8 is turned off. Stage V (the first node Q(n) and the output terminal G(n) are maintained at low voltage level): CK2 provides high voltage level, T9 is turned on, the second node P(n) is charged to high voltage level, T6 and T7 are turned on and thus continuously pull down the first node Q(n) and the output terminal G(n) respectively to the constant low voltage level VGL, the second node P(n) is continuously maintained at high voltage level due to the storage function of the second capacitor C2, T6 and T7 are continuously turned on in one frame period and thus maintain the first node Q(n) and the output terminal G(n) at low voltage level.
It is not difficult to see from FIG. 2 that the corresponding high voltage level of the second node P(n) approaches the constant high voltage level VGH (the high voltage level of the second node P(n) can be adjusted for a certain degree by using T9) and the low voltage level thereof is the constant low voltage level VGL (it cannot be altered). In the afore-described existing GOA electric circuit, the second node P(n) is always in a high-voltage-level state, that is, T6 and T7 are always in a turned-on state. T6 and T7 are operated for a long time and this results in a shift of the threshold voltages (Vth shift) of the two key thin-film transistors T6 and T7 and this decreases the stability of the circuit, thereby causing abnormal output of the GOA electric circuit.
Therefore, there is a need to provide a new GOA electric circuit for improving the stability of GOA electric circuit.